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Chasing MOSFETs and Sleep Current: Notes From a Latching Power-Switch Build
I've been trying to work out a latching power-switch circuit using a MOSFET, and it's been a humbling process. I derived an expression for Vgs that came out independent of the battery voltage, which doesn't match what I actually observe on the bench — I suspect my assumption of no voltage drop across drain and source was the mistake. I drew up a diagram of the circuit (currently with a hole where the MCU should be, since I fried mine) and shared it, but after checking things over I had to admit I simply don't understand MOSFETs yet. Along the way I found a video using a BJT and an opto-isolator instead, which avoids the voltage drop a FET gives you, and eventually concluded that PMOS + NPN is the way to go, since that's how every latching circuit I come across is built. In parallel I've been procrastinating on assembling my CurrentRanger — I thought I had a spare OLED but I don't, so I'll have to dig into the serial interface instead.
Description
What I'm building
The core of this is a latching power switch for a battery-powered project. The idea is to have a circuit that can be switched on and then held on, with the MCU able to control its own power.
The MOSFET problem
I derived an expression for Vgs and it came out independent of the battery's voltage. That doesn't match what I see in real life, which is the clearest sign possible that my model is wrong somewhere. My best guess is that I assumed no voltage drop across drain and source, and that this was a mistake.
I promised the group a diagram and drew one up the following day. It isn't fully accurate, because there's currently a hole in the circuit in lieu of the MCU — I fried it.
After going back and checking, I had to just say it plainly: I don't understand MOSFETs. Stavros was kind enough to welcome me to the club. I also asked him what he uses to simulate circuits, since he'd mentioned simulating his at some point.
At that stage I decided to stop, since I had some real-life things I'd been procrastinating on, and I wanted to get more familiar with MOSFETs before going further.
An alternative approach: BJT and opto-isolator
I came across a video showing the job done with a BJT and an opto-isolator. The appeal there is that with the opto-isolator you don't get the voltage drop you'd get with a FET — which, at least in my case, would work around the voltage drop from the FET that seems to be at the heart of my confusion.
Where I landed
Coming back to it later, the pattern became clear: it does look like PMOS + NPN is the way to go. Every time I encounter a latching circuit, that's how it's made. I passed the reference along to Stavros, who was working on a pendant of his own and had tried my pin idea for powering his mic.
Side project: the CurrentRanger
I've also been procrastinating on the assembly of my CurrentRanger. I'd thought I had a spare OLED for it, but I don't — so I'll have to dig into the serial interface instead.
Still open
- Getting properly comfortable with MOSFETs, including where exactly my Vgs derivation goes wrong.
- Finding a circuit simulator I like.
- Replacing the fried MCU so the diagram matches the real thing.
- Assembling the CurrentRanger and working out its serial interface.