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Chasing MOSFETs and Sleep Current: Notes From a Latching Power-Switch Build
I've been trying to work out a latching power-switch circuit using a MOSFET, and it's been a humbling process. I derived an expression for Vgs that came out independent of the battery voltage, which doesn't match what I actually observe on the bench — I suspect my assumption of no voltage drop across drain and source was the mistake. I drew up a diagram of the circuit (currently with a hole where the MCU should be, since I fried mine) and shared it, but after checking things over I had to admit I simply don't understand MOSFETs yet. Along the way I found a video using a BJT and an opto-isolator instead, which avoids the voltage drop a FET gives you, and eventually concluded that PMOS + NPN is the way to go, since that's how every latching circuit I come across is built. In parallel I've been procrastinating on assembling my CurrentRanger — I thought I had a spare OLED but I don't, so I'll have to dig into the serial interface instead.